Documento de conferencia

Towards a field configurable non-homogeneous multiprocessors architecture

| |
Resumen

Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design.

Palabras clave
embedded multiprocessing
system-on-chip
distributed heterogeneous embedded system
programmable logic
IP cores
system-level design
http://creativecommons.org/licenses/by/4.0/

Esta obra se publica con la licencia Creative Commons Attribution 4.0 International (BY 4.0)

item.page.license
Imagen en miniatura