Towards a field configurable non-homogeneous multiprocessors architecture
Towards a field configurable non-homogeneous multiprocessors architecture
| cic.isFulltext | true | es |
| cic.isPeerReviewed | true | es |
| cic.lugarDesarrollo | Instituto de Investigación en Informática | es |
| cic.version | info:eu-repo/semantics/publishedVersion | es |
| dc.date.accessioned | 2015-12-30T16:29:37Z | |
| dc.date.available | 2015-12-30T16:29:37Z | |
| dc.identifier.uri | https://digital.cic.gba.gob.ar/handle/11746/1546 | |
| dc.title | Towards a field configurable non-homogeneous multiprocessors architecture | en |
| dc.type | Documento de conferencia | es |
| dcterms.abstract | Standard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design. | en |
| dcterms.creator.author | Jaquenod, Guillermo A. | es |
| dcterms.creator.author | Villagarcía Wanza, Horacio Alfredo | es |
| dcterms.creator.author | De Giusti, Marisa Raquel | es |
| dcterms.extent | 6 p. | es |
| dcterms.identifier.url | Documento Completo | es |
| dcterms.isPartOf.issue | 5th World Multi-conference on Systemics, Cybernetics and Informatics | es |
| dcterms.isPartOf.series | World Multi-conference on Systemics, Cybernetics and Informatics (SCI2001) | es |
| dcterms.issued | 2001 | |
| dcterms.language | Inglés | es |
| dcterms.license | Attribution 4.0 International (BY 4.0) | es |
| dcterms.relation | Informe científico de investigador: De Giusti, Marisa Raquel (2000-2002) | es |
| dcterms.subject | embedded multiprocessing | es |
| dcterms.subject | system-on-chip | es |
| dcterms.subject | distributed heterogeneous embedded system | es |
| dcterms.subject | programmable logic | es |
| dcterms.subject | IP cores | es |
| dcterms.subject | system-level design | es |
| dcterms.subject.materia | Ciencias de la Computación | es |
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