A fast CORDIC co-processor architecture for digital signal processing applications
| cic.isFulltext | true | es |
| cic.isPeerReviewed | true | es |
| cic.lugarDesarrollo | Instituto de Investigación en Informática | es |
| cic.version | info:eu-repo/semantics/publishedVersion | es |
| dc.date.accessioned | 2016-09-05T12:03:37Z | |
| dc.date.available | 2016-09-05T12:03:37Z | |
| dc.identifier.uri | https://digital.cic.gba.gob.ar/handle/11746/4141 | |
| dc.title | A fast CORDIC co-processor architecture for digital signal processing applications | en |
| dc.type | Documento de conferencia | es |
| dcterms.abstract | The coordinate rotational digital computer (CORDIC) is an arithmetic algorithm, which has been used for arithmetic units in the fast computing of elementary functions and for special purpose hardware in programmable logic devices. This paper describes a classification method that can be used for the possible applications of the algorithm and the architecture that is required for fast hardware computing of the algorithm. | en |
| dcterms.creator.author | Giacomantone, Javier | es |
| dcterms.creator.author | Villagarcía Wanza, Horacio Alfredo | es |
| dcterms.creator.author | Bria, Oscar N. | es |
| dcterms.description | Área: Redes - Sistemas Operativos - Sistemas de Tiempo Real - Arquitectura de Procesadores | es |
| dcterms.extent | 9 p. | es |
| dcterms.identifier.url | Documento completo | es |
| dcterms.isPartOf.issue | VI CACIC | es |
| dcterms.isPartOf.series | Congreso Argentino de Ciencias de la Computación | es |
| dcterms.issued | 2000-10 | |
| dcterms.language | Inglés | es |
| dcterms.license | Attribution 4.0 International (BY 4.0) | es |
| dcterms.subject | computer architectures | en |
| dcterms.subject | CORDIC | en |
| dcterms.subject | computer arithmetic | en |
| dcterms.subject | hardware algorithms | en |
| dcterms.subject | digital signal processing applications | en |
| dcterms.subject.materia | Ciencias de la Computación | es |
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